To continue!
I've created a new component, vji_component. In the planned pulse measurement testbench, this component will be the bridge between the host system and the pulse generator logic. The general purpose of vji_component is to provide one or more host-accessible input or output signals, while hiding all the complexity of using the sld_virtual_instance.
For components I've written previously, I've provided a handful of test cases. These test cases were simple: each one generates a particular instance of the component, and then compares the generated HDL against a "known good" reference HDL file. One problem with this approach is that my "known good" files have not actually been verified for correct function. Still, this method lets me proceed confidently with component changes which should not result in changed output. vji_component follows the same basic flow that I've established with previous components, but with one additional test feature: a system test.
In the system test, a vji_component instance is configured to have an input and output signal of width 24 (by default; the width is configurable). The output signal wires to the input signal through inverters. A tcl script drives random numbers into the writedata port, reads back the inverted signal on the readdata port, and verifies the value. The block diagram shows what's going on (sorry about that "inv" block - my attempt at an ASCII inverter symbol ended in failure).
With this new system test, I'm taking the opportunity to create the entire system from as few source files as possible, under control of a Makefile. The system top-level is generated by a europa_module_factory-derived perl module and looks exactly like any other component. (I have come to realize that my use of the word "component" is not standard. When I say "component" I just mean some logic with optional sub-instances. Just about any HDL hierarchy is a "component", so maybe I need a different word.)
The test system source files are as follows:
- make_quartus_project.tcl: creates the quartus project, makes pin assignments, etc.
- vji_test_system/vji_test_system.pm: perl module for the system "component". One parameter is provided, "datawidth"
- compile_quartus_project.tcl: compiles the project in quartus
- test.tcl: functional test: a script to write, read and verify
- Makefile: targets are:
- qp: call a tcl script to create the quartus project
- hdl: create the HDL
- sof: compile to bitstream (sof)
- pgm: program the FPGA
- test: test the system by writing, reading and verifying
- clean: destroy the evidence
The upshot of all this: 5 source files encode the system and test scripts. Typing "make" runs everything and reports any errors.
Zip archive of the vji_component and associated tests.